1. Field of the Invention
The invention relates to the design of integrated circuit (IC) power amplifier systems and more particularly the biasing of the signal path of IC power amplifier systems.
2. Prior Art
Design of amplifiers for various frequency ranges (low, mid, high and radio frequency) using various semiconductor processing technologies (bipolar, CMOS, GaAs, etc.) and in different configurations (single-ended, differential, quadrature, common source, common emitter, common gate, common base, etc.) is well documented in the art. In the art there are described three ways of biasing an amplifier stage: voltage bias, current bias and a hybrid technique using both voltages and currents.
Biasing of low and moderate power amplifiers is relatively straightforward and can be done in a variety of ways. Biasing of high-power, e.g., around or over one watt, amplifiers (PAs) in general, and high-frequency, e.g., around or over one giga Hertz, PAs in particular, is a more complex and challenging problem. This is particularly true with respect of high efficiency performance when little power should be lost on the biasing circuit.
Today the cellular handset PA market is still dominated by GaAs solutions for the radio frequency (RF) signal path that allow single devices, un-cascoded amplifier stages to be used while handling the large voltage swing of the high-power PA. FIG. 1 shows a typical system level schematic diagram 100 of a cellular PA system using RF integrated circuit (IC) 120, e.g., using GaAs. This integrates the RF signal path driving stages 122 through 124 (it should be noted that while two stages are shown a plurality of such stages may be used) and the output stage 126. The IC 120 may further include a bias circuit for the signal path stages of IC 120. A control IC 110 integrates in a separate device the PA power control that is typically comprised of a power sensing and estimation unit 118 and a drain power control 116 that provides the PA output, typically via a coil 119, the necessary bias for the output stages of IC 120. The IC 110 may further contain the supply voltage for earlier stages of the signal path IC 120.
The two chip solution mandates a simple interface between the RF signal path IC 120 and the power control IC 110. This restricts the PA power control scheme to a single control port. The fact that shipping RF signal between IC 110 and IC 120 is hard to do in the context of high-efficiency, thereby restricting the IC 110 to the drain (collector) PA power control scheme which uses baseband sensing. Using high impedance lines between IC 110 and IC 120 is not a good choice due to its high sensitivity to parasitic coupling.
Therefore, in view of the deficiencies of the prior art solutions it would be valuable to provide a solution that overcomes these deficiencies. Preferably the solution would allow the integration of the power control into a single IC while maintaining the required performance for high frequency operation at the PA stages. It would be further advantageous if the solution can be implemented in CMOS technology.